How to make simple Makefile

In programming is very necessary to compile the application quickly after applying some changes in your source code. In other words, after modification you need to compile your code again to test it to see is it working or not. It is obvious that just some parts of the code have been changed not all parts.

Therefore, you do not need to compile the unchanged parts which will take a lot of time to compile the entire application when your code is so big. In addition, you do not want to set and type many parameters to compile your code again and again.

If you use an IDE to develop your application, most of them do above tasks for you easily and there is no worry for you. On the other hand if you write your code just in text editor and compile it via command line, you need to handle those matters by your self especially when your application is huge. For small codes most of the time no need to be worry since there is no need to test the code many times and rewrite parts of the code.

In both Linux and Windows you can automate setting parameters and compiling process. In Windows platform you can do it with creating batch files but this post does not cover it. In Linux you can make a simple text file which is called as Makefile to do all mentioned tasks for you. Makefile is a simple text file and can be created with text editors. This file has certain structure or grammar such as C/C++ or any other programming languages source codes. Makefile also mostly contains Linux commands and it uses Make utility to start execution. So after creating the file you just need to set the parameters once and it does the rest of the work. Furthermore, it saves a lot of time with not compiling the unchanged parts of the code.

The following part demonstrates about making a very small and simple make file for compiling C/C++ languages. The below code shows a simple Makefile,

all:

         g++ hello.cpp -o hello

The above code is the most basic Makefile which just compiles hello.cpp file and hello is the compiled file (executable file). It is clear that the above code is the same as the compiling command in terminal and just ‘all:’ is added.

Now if you want to compile bunch of related files together and make a executable file you can use the following code,

all:

         g++ main.cpp sum.cpp sub.cpp -o main

In addition, you can break the above process to sub processes as well. It means that maybe you want to compile just ‘hello.cpp’ on especial occasions and other time all files. See the below example,

all: main.o sum.o sub.o

        $(CC) main.o sum.o sub.o -o MyApp

main.o: main.cpp

        $(CC) $(CFLAGS) main.cpp

sum.o: sum.cpp

        $(CC) $(CFLAGS) sum.cpp

sub.o: sub.cpp

        $(CC) $(CFLAGS) sub.cpp

The above example is called dependencies in Makefile. It looks complex but it is really really simple. It just follows the rule of calling functions in programming. Let’s give an example for better understanding. For instance, you want to compile all three files (main.cpp, sum.cpp, and sub.cpp) together, the procedure is done in the following order.

1- Firstly for compling all files we need to compile three object files (main.o, sum.o, sub.o).

2- When make faces with ‘main.o’, it will jump to related part and executed the command in front of it.

3- The same procedure will be done for all files until all of them will be ready.

4- Finally, the command in front of ‘all’ will be executed which at first was depended to compilation of ‘main.cpp’, ‘sum.cpp’, and ‘sub.cpp’.

Now if you just want to compile for example ‘sub.cpp’, you just need to write the following command for executing sub compilation part.

$ make sub

Sometimes, you want to remove all compiled files for different purposes. You can add the following line into your Makefile.

clean:

        rm -rf *o main

As you can see, the above line is just a Linux command. For executing clean part you need to type the below line,

$ make clean

In the last example two ‘CC’, ‘CFLAGS’ variables were used. The idea of using variable is that, you change them once and it will be applied in the entire of Makefile. Otherwise, you should change the parameters manually for each entry. For better understanding of using variable look at the example,

CC=g++

        CFLAGS=-c -Wall

all: main.o sum.o sub.o

        $(CC) main.o sum.o sub.o -o MyApp

main.o: main.cpp

        $(CC) $(CFLAGS) main.cpp

sum.o: sum.cpp

        $(CC) $(CFLAGS) sum.cpp

sub.o: sub.cpp

        $(CC) $(CFLAGS) sub.cpp

In mentioned example firstly, the variables are set then they have been used. In addition, you can define a variable for holding ‘main.o sum.o sub.o -o hello’ line.

More information can be found in the following websites.
http://www.cs.colby.edu
http://mrbook.org

send your idea and information to kasra.madadipouya@geeksweb.tk

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